A successive approximation analog-to-digital converter generally comprises a capacitor array which has precision thereof determines precision of the successive approximation Analog-to-Digital Converter. Three problems need to be solved in regard to successive approximation Analog-to-Digital Conversion.
1. Structure problem of capacitor array
a. If single-segment architecture is adopt, the number of unit capacitor is expressed as follows:2Ns  (1)
Wherein, Ns denotes the resolution of A/D converters. The number of unit capacitors increases at an exponential rate as the resolution of A/D converters increases. The size and power consumption of chip increases when the resolution of A/D converters Ns increases. Normally, capacitor mismatch error needs to be corrected when the resolution of A/D converters Ns is larger than 10.
b. If segment architecture is adopted, the number of unit capacitors dramatically decreases. For instance, when Ns is even number, the structure of capacitor arrays is divided into two identical structures, then the number of unit capacitors is expressed as follow:
                              2          ·                      2                                          N                s                            2                                      +        1                            (        2        )            
In doing so, the number of unit capacitors dramatically decreases especially when Ns is large. Multiple-segment structure tends to bring mismatch errors of equivalent capacitors. Therefore, capacitor mismatch error correction is in need for multiple-segment structure which is more complicated than that for single-segment architecture. Traditional capacitor mismatch error correction works to use compensation capacitor array to compensate capacitor mismatch error. That is to say, when a capacitor is involved in the addition of electric charges, a corresponding compensation capacitor array is added to compensate the variation of electric charges caused by mismatch error. The compensation capacitor array features the resolution less than 1 least significant bit (LSB). Therefore, if Ns is large, compensation capacitor array tends to apply a complicated structure to realize high resolution for compensation, which is too complicated to be realized.
A traditional successive approximation analog-to-digital converter works to apply digital correction by recording each capacitor's weight. Even though the weight of each capacitor can be correctly measured, code omission occurs when the weight of the high significant bit is larger than the sum of the weights of the rest bits plus 1 LSB. Take a 4 bit A/D converter as an example. Its actual weights are 9, 3, 2 and 1. The input/output values are correspondingly listed as follows:
In  0  1   2   3   4   5   6   7  Out  0  1   2   3   4   5   6   6  In  8  9  10  11  12  13  14  15  Out  6  9  10  11  12  13  14  15  
Wherein, the output code 7 and 8 are missing.
Therefore, an improved structure needs to be made for successive approximation analog-to-digital (A/D) converters.